The present invention generally relates to die packaging, and more particularly relates to a high-voltage flip-chip component package and a high-voltage flip-chip packaging process.
Die packaging has continued to receive a significant amount of attention from designers and manufacturers of electronic products. This attention is based upon the market demand for products with greater efficiency, higher performance, and smaller dimensions. The market demand for smaller dimensions is driven at least to some extent by portable electronic product applications, such as Implantable Medical Devices (IMDs).
As the dimensions of an IMD package become smaller and smaller, and as more and more components are added to such a device, the area that is available for additional components is reduced within the IMD package. Furthermore, as the dimensions of the components are also shrinking, it is desirable to improve the use of the dimensions within the IMD package. While die packages have been designed and manufactured that improve the utilization of all three dimensions within electronic packages, including portable electronic packages such as IMD packages, improvements are sought to the die package and the methods of forming the die package.
Flip-chip technology is a semiconductor fabrication technology that allows the overall package size to be made very compact. The flip-chip package configuration differs from the conventional ones particularly in that it mounts the die in an upside-down manner over the chip carrier, or substrate, and electrically couples the die to the substrate by means of solder bumps provided on the active surface of the die. Since minimal or no bonding wires are required, which would otherwise occupy much layout space, the overall size of the flip-chip package can be made very compact as compared to conventional types of electronic packages.
However, high voltage die used in IMD packages present challenges in flip-chip packaging. High voltage die refers to an electronic component or device that is operable with a potential greater than about 50 volts across any two electrical terminals or contacts of the component. Such high voltage components may be further operable at DC voltages greater than about 100 volts, and even further may be operable at DC voltages greater than about 500 volts, 1000 volts and even greater, perhaps as great as 1600 or more volts. High voltage die may include devices such as Field Effect Transistors (FETs), Metal Oxide Semiconductor (MOS) FETs (MOSFETs), Insulated Gate FETs (IGFETs), thyristors, bipolar transistors, diodes, MOS-controlled thyristors, resistors, capacitors, etc.
At high temperatures, such as temperatures above about 80xc2x0 C., the underfill used in the flip-chip package may become polarized and/or ions in the underfill may be attracted to the high voltage die. Such phenomena may cause detrimental electrical performance changes, such as, for example, leakage current that can cause a device in the off-state to switch to the on-state.
In addition, circuit traces formed within the substrate upon which the high-voltage die is mounted create electric fields. If the circuit traces are not routed deep enough within the substrate, the electric fields may be sufficiently close to the die and of sufficient strength to negatively influence the performance of the die.
Accordingly, it is desirable to provide an improved flip-chip package and an improved flip-chip packaging process. It is further desirable to provide an improved flip-chip package for high voltage components and an improved flip-chip packaging process for packaging high voltage components. Furthermore, other desirable features and characteristics of the present invention will become apparent from the subsequent detailed description of the invention and the appended claims, taken in conjunction with the accompanying drawings and this background of the invention.
According to an exemplary embodiment of the invention, there is provided a flip-chip package comprising a substrate having at least one layer and a component flip-chip mounted to the substrate, the component having a field termination ring. The flip-chip package further comprises a shield plane interposed between the at least one layer of substrate and the field termination ring.
According to another exemplary embodiment of the invention, there is provided a flip-chip packaging process. The process comprises the steps of providing a substrate having at least one layer and providing a component having a field termination ring. The process further includes the steps of flip-chip mounting the component to the substrate and interposing a shield plane between the at least one layer of the substrate and the field termination ring.